Field of the Disclosure
The present disclosure relates generally to caching in processing systems and, more particularly, to selection of cache lines for replacement in processing systems.
Description of the Related Art
A processing system may utilize a faster, smaller memory as a software-managed cache for caching data from a larger, slower memory. When a memory location is accessed repeatedly, a copy of the contents of the memory location may be stored to a corresponding line of the cache. When the cache is over-subscribed, certain cache lines are selected for eviction to make room for incoming cache lines. Most conventional cache line replacement algorithms used to select the cache lines for eviction are implemented in hardware and are based on a simple least recently used (LRU) algorithm that relies on only a relatively short window of activity. Furthermore, the replacement algorithm is fixed, that is, cannot be updated or changed. Moreover, such hardware-implemented algorithms require storage of access information in a cache tag per cache line, thereby reducing the amount of the faster, smaller memory that can be utilized for caching data, as well as increasing the cost of implementation.